Integrated circuits (large scale, very large scale, etc., including system-on-chip (SOC) configurations) employ one or more master (i.e., primary) clock signals to synchronize logic operations. Clock distribution systems distribute master clock signals from sources of periodic signals to circuit destination nodes. To synchronize operations of integrated circuits, the clock distribution systems are designed such that the clock transitions (i.e., rising edges and/or falling edges) at each destination node within the integrated circuit occur substantially simultaneously. However, variations in the clock signal occur at different nodes due to physical features of the clock distribution system (e.g., distance from the source and performance variations of components). These clock signal variations are called “skew.” If the design of a clock distribution system results in skew that exceeds margins permitted by timing requirements of the integrated circuit's design, the integrated circuit may not function as intended.
Further, the clock distribution system consumes a large portion of the total system power of the integrated circuit. Resonant clocking is a technique that reduces the power required to drive the clock distribution system by recycling energy using coupled LC (inductance and capacitance) oscillator circuits which are incorporated in the clock distribution system. Oscillations of resonant clocking systems are tuned to specific frequencies. As such, integrated circuits (e.g., processors) that operate at different frequencies must be able to enable and disable resonant clocking.